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VLSI - STA

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Edusaksham has launched a new product for those who wants to crack "Static Timing Analysis" (STA) Interview. This program is designed to help VLSI aspirants understand the basic and advance concepts required for Semiconductor Industry. It will help them identify their strength and areas of improvements to re-build their concepts. 

15 papers related to "Static Timing Analysis" which helps in building fundamentals and concepts.

Duration

- Validity of Assessment tool is for 1 year from the date of enrollment

Certification

Certificate of Completion

Key Features

  • Papers based on Basics to Advanced STA concepts
  • 15 Practice papers
  • Innovative Assessment tool
  • Detailed Analytics  
  • Identification of strong and weak area

Who can attend

  • B. Tech (3rd & 4th-year students)
  • M. Tech (1st & 2nd-year  students)
  • Professionals with 0-4 years of experience or anyone who wants to build strong  conceptual knowledge 

 Assessment Tool:

  • Practice Paper: 15 papers
  • Topics covered:
    • Delay, Timing concepts, Timing Arc, Timing path and exceptions, Timing checks, Setup and Hold Time, Setup and Hold Violation
  • Analytical report

VLSI - STA++

Static Timing Analysis ++ program is designed to help VLSI aspirants understand the basic and advance concepts required for Semiconductor Industry. It will help them identify their strength and areas of improvements to re-build their concepts. An innovative assessment technique along with personalized online classes is a unique feature for VLSI Job Aspirants.

Duration: (10 weeks program)

- 40 Hours online classes
- Validity of Assessment tool is for 1 year from the date of enrollment

Certification

Certificate of Completion: After completion of online classes

Key Features

  • 40 hours online classes
  • Guest classes by Industry person
  • Basics to Advanced STA concepts
  • Interactive Sessions
  • Discussion on Timing projects
  • 15 Practice papers
  • Innovative Assessment tool
  • Re-attend missing online classes
  • Certificate of Completion
  • 100% Placement Assistance

Training Delivery Model

Interactive online classes for 40 hours with emphasis on regular assessment and personalized feedback

Who can attend

  • B. Tech (3rd & 4th year students)
  • M. Tech (1st & 2nd year  students)
  • Professionals with 0-4 years of experience or anyone who wants to build their conceptual knowledge strong

Course Content

Module 1: Timing Paths

  • False and multi-cycle path concepts along with another type of Timing paths

Module 2: Timing Arc

  • Different type of Timing Arc
  • How to read the different information from Timing Libraries

Module 3: Delay

  • Cell Delay / Net Delay
  • Wire Load Model
  • Transition Delay / Propagation Delay
  • Delay calculation in Path Base analysis vs. Graph Base Analysis
  • Different type of Min and Max Delay calculation
  • Introduction of SDF
  • Delay because of Parasitic (RC)
  • Delay calculation based on SPEF file
  • NLDM (Non-Linear Delay Model)
  • CCS timing library Delay concepts
  • How delay changes because of different operating conditions, PVT corners, and RC corners?

Module 4: Setup and Hold Time / Violation

  • Basic Concepts and terminology (Launch/Capture paths, Slack)
  • In different circuits, how to calculate the timing Violations
  • How to calculate Setup and hold time of a system/macro
  • Path basis analysis vs. Graph-based analysis
  • OCV / AOCV basis analysis
  • PVT corner based analysis
  • How to solve Timing violations
  • Effect of Drive strength
  • Effect of size of gate or Net
  • Fan-out/Fan-In
  • Adding or removing buffer
  • Placement of the gate

Module 5: Timing Models

  • Basic understanding of QTM / ILM / ETM
  • Basic understanding of Hyper scale models (Advance Timing technique)

Module 6: Clocks

  • Different terminologies (Clock Period, Latency, Virtual Clock, Generated Clock, Uncertainty, Jitter)
  • Synchronous vs. Asynchronous Clocks
  • Clock Gating
  • How to generate different type of generated clocks (like divide by 2 and all)
  • Clock Skew

Module 7: Clock Network

  • Clock Mesh
  • Different configuration,
  • Advantage and disadvantage
  • Clock Tree
  • Different type of tree
  • Advantage and Disadvantage

Module 8: SI Effect

  • Effect of Crosstalk on Timing analysis
  • What's the cross talk
  • Reasons of cross talk

Module 9: Parasitic Extraction

  • Only those concepts, which are important from the timing perspective.
  • Different type of caps (Coupling cap, fringe cap), Shielding effect, Metal fill (dummy metal)
  • Net Delay, Transition Delay

Module 10: ECO concepts

  • Why it's required?
  • How usually it is done?
  • What’s the advantage and disadvantage of this?

Module 11: DMSA

  • Multi-Scenario Analysis
  • What is multi Scenario
  • What's the importance
  • Distributed Analysis
  • DMSA
  • Challenges
  • Advantage
  • How to read reports
  • Special Variables
  • Effect on constraint generation or analysis or reporting

Module 12: Other Concepts

  • OCV (On Chip Variation)
  • AOCV (Advance On-Chip Variation)
  • How to set derting (globally, locally)
  • Clock Re-convergence Pessimism Removal (CRR and CRPR)

Assessment Tool (Includes all features of STA):

  • Practice Paper: 15 papers
  • Topics covered:
    • Delay, Timing concepts, Timing Arc, Timing path and exceptions, Timing checks, Setup and Hold Time, Setup and Hold Violation
  • Analytical report

About Trainer:

Puneet VLSI

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